1. Field of the Invention
The present invention generally relates to integrated circuit technology, and more particularly to electronic circuitry having different trip points for the rising and falling edges of the input signal.
2. Description of the Related Art
Prior art devices employ analog circuitry which provide an output pulse having rising and falling edges, which are independently delayed from the corresponding rising and falling edges of an input pulse. U.S. Pat. No. 4,812,687, the complete disclosure of which is herein incorporated by reference, describes such a circuit, wherein the circuit function occurs by using a charging capacitor, which drives a Schmitt trigger.
In this prior art circuit, the charge on the capacitor is determined by a first constant current source and a switch responsive to the rising edge of the input pulse, and a corresponding second constant current source and a switch responsive to the falling edge of the input pulse. Furthermore, it is taught that by varying the width-to-length ratio of the device, the value of the charge-up current and discharge current can be controlled.
Those skilled in the art would readily appreciate the functions of a Schmitt trigger which provides a low state output signal when its input receives a voltage input equal to or less than a low voltage trigger value, and a high state output signal when its input receives a voltage input equal to or higher than a high trigger value. Additionally, for input voltages between the low trigger value and the high trigger value, the Schmitt trigger remains in an unswitched condition.
Other prior art circuits teach various ways of controlling the input signal, thereby controlling the corresponding rise and fall times of the signal, such as U.S. Pat. No. 4,488,060 (teaching a high voltage ramp rate control circuit providing a controllable ramp rate action useful in high voltage power supplies); U.S. Pat. No. 5,534,811 (teaching a driver circuit having an input terminal fed by a logic signal and producing a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver); U.S. Pat. No. 5,982,218 (teaching an input circuit provided in a semiconductor integrated circuit used in a high-speed small-amplitude signal transmission system having a ratio of gate length to gate width in a PMOS transistor of 1:4, and a ratio of gate length to gate width in a NMOS transistor of 1:40); and U.S. Pat. No. 6,069,511 (teaching a signal shaping circuit for use in a transmission line driver, wherein the input is a pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which triggers the delay circuit to produce a second sequence of multiple delayed outputs, and wherein, by controlling the first and second delayed output, the rise and fall times of the output signal can be precisely controlled), the complete disclosures of which are herein incorporated by reference.
However, the conventional circuits often result in poor power dissipation rates and, as such, may not be applicable in low power applications. Furthermore, the conventional circuits do not provide for a different trip point for the rising and falling edges of the input signal.
This capability is very important because it provides the ability to control the timing relationship between the output transitions of the comparator corresponding to the rising and falling edges of the input signal. Furthermore, it allows for the control of the delay between rising and falling output transitions out of the comparator. It also provides the capability to vary the positive or negative pulse width of the comparator output signal. Thus, there is a need for a comparator having different trip points for the rising and falling edges of the input signal which dissipates less power than the conventional comparator devices, and which is ideal for use in low power applications.